MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
10-46 Freescale Semiconductor
Table 10-13. Changes to MPC5553/5554 RM for Rev. 5.0 Release
Description of Change
• SECTION 10.5.5.2 Ensuring Coherency
Added the following sentence before GetResource source code:
Processor recognition of interrupts must be enabled before executing the GetResource code sequence.”
• SECTION 10.3.1.3 INTC Interrupt Acknowledge Register (INTC_IACKR)
Removed the first paragraph from the Note:
“The INTC_IACKR must not be read speculatively while in software vector mode. Therefore, for future compatibility, the TLB
entry covering the INTC_IACKR must be configured to be guarded.”
• TABLE 10-2. INTC Memory Map
Added the following note at the end of this table:
“To ensure compatibility with all PowerPC processors, the TLB entry covering the INTC memory map must be configured
as guarded, both in software and hardware vector modes.
• In software vector mode, the INTC_IACKR must not be read speculatively.
• In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before the interrupt acknowledge
signal from the processor asserts.
• SECTION 10.4.2.1.4 Priority Comparator Submodule
Added the following paragraph to this section:
One consequence of the priority comparator design is that once a higher priority interrupt is captured, it must be
acknowledged by the CPU before a subsequent interrupt request of even higher priority can be captured. For example, if
the CPU is executing a priority level 1 interrupt, and a priority level 2 interrupt request is captured by the INTC, followed
shortly by a priority level 3 interrupt request to the INTC, the level 2 interrupt must be acknowledged by the CPU before a
new level 3 interrupt will be generated.
• SECTION 10.5.5.2 Ensuring Coherency
Moved the text in Section 10.5.5.2: Ensuring Coherency under a new “Section 10.5.5.2.1: Interrupt with Blocked Priority”.
Added a new “Section 10.5.5.2.2: Raised Priority Preserved”.
• TABLE 10.9 INTC: Interrupt Request Sources
Removed ETPU_MCR[MGEB] and ETPU_MCR[ILFB] from the “Source MPC5553” column under eTPU_A for hardware
vector mode offset 0x0430.
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