MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 11-11
11.1.4.2 External Reference Mode
This external reference mode functions the same as crystal reference mode except that EXTAL_EXTCLK
is driven by an external clock generator rather than a crystal oscillator. Also, the input frequency range
(F
ref_ext
) in external reference mode is the same as the input frequency reference range (F
ref-crystal
) in the
crystal reference mode. To enter external reference mode, the default FMPLL configuration must be
overridden by following the procedure outlined in Section 11.1.4, “FMPLL Modes of Operation.” A block
diagram illustrating external reference mode is shown in Figure 11-3.
NOTE
In addition to supplying power for the CLKOUT signal, when the FMPLL
is configured for external reference mode of operation, the V
DDE5
supply
voltage also controls the voltage level at which the signal presented to the
EXTAL_EXTCLK pin causes a switch in the clock logic levels. The
EXTAL_EXTCLK will accept a clock source with a voltage range of 1.6V
to 3.6V, however the transition voltage is determined by V
DDE5
supply
voltage divided by 2. As an example, if V
DDE5
is 3.3V, then the clock will
transition at approximately 1.6V. The V
DDE5
supply voltage and the voltage
level of the external clock reference must be compatible, or the device will
not clock properly.
11.1.4.3 Bypass Mode
In FMPLL bypass mode, the FMPLL is completely bypassed and the user must supply an external clock
on the EXTAL_EXTCLK pin. The external clock is used directly to produce the internal system clocks.
In bypass mode, the analog portion of the FMPLL is disabled and no clocks are generated at the FMPLL
output. Consequently, frequency modulation is not available. In bypass mode the pre-divider is bypassed
and has no effect on the system clock. The frequency in bypass mode is F
ref_ext
.
To enter bypass mode, the default FMPLL configuration must be overridden by following the procedure
outlined in Section 11.1.4, “FMPLL Modes of Operation.” A block diagram illustrating bypass mode is
shown in Figure 11-2.
11.1.4.4 Dual-Controller Mode (1:1)
FMPLL dual-controller mode is used by the slave MCU device of a dual-controller system. The slave
FMPLL will facilitate skew reduction between the input and output clock signals. To enter dual-controller
mode, the default FMPLL configuration must be overridden by the procedure outlined in Section 11.1.4,
“FMPLL Modes of Operation.”
In this mode, the system clock runs at twice the frequency of the EXTAL_EXTCLK input pin and is phase
aligned. Note that crystal operation is not supported in dual-controller mode and an external clock must be
provided. In this mode, the frequency and phase of the signal at the EXTAL_EXTCLK pin and the
CLKOUT pin of the slave MCU are matched. A block diagram illustrating dual-controller mode (1:1) is
shown in Figure 11-6.
Frequency modulation is not available when configured for dual-controller mode for both the master and
slave devices. Enabling frequency modulation on the device supplying the reference clock to the slave in
dual-controller mode will produce unreliable clocks on the slave.
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