MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
11-26 Freescale Semiconductor
NOTE
Following these steps will produce immediate changes in supply current,
thus the user should ensure that the power supply is sufficiently decoupled
with low ESR capacitors.
Here are the steps to program the clock frequency without frequency modulation:
1. Determine the appropriate value for the PREDIV, MFD, and RFD fields in the synthesizer control
register (FMPLL_SYNCR). Remember to include the F
m
if frequency modulation is to be
enabled. Note that the amount of jitter in the system clocks can be minimized by selecting the
maximum MFD factor that can be paired with an RFD factor to provide the desired frequency. The
maximum MFD value that can be used is determined by the ICO range. See the MPC5553
Microcontroller Data Sheet and the MPC5554 Microcontroller Data Sheet for the maximum
frequency of the ICO.
2. Change the following in FMPLL_SYNCR:
a) Make sure frequency modulation is disabled (FMPLL_SYNCR[DEPTH] = 00). A change to
PREDIV, MFD, or RATE while modulation is enabled will invalidate the previous calibration
results.
b) Clear FMPLL_SYNCR[LOLRE]. If this bit is set, the MCU will go into reset when MFD is
written.
c) Initialize the FMPLL for less than the desired final system frequency (done in one single write
to FMPLL_SYNCR):
— Disable LOLIRQ.
— Write FMPLL_SYNCR[PREDIV] to a desired final value.
— Write FMPLL_SYNCR[MFD] to a desired final value.
— Write the RFD control field to a desired final RFD value + 1.
3. Wait for the FMPLL to lock by monitoring the FMPLL_SYNSR[LOCK] bit. Refer to
Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR),” for memory
synchronization between changing FMPLL_SYNCR[MFD] and monitoring the lock status.
4. Initialize the FMPLL for the desired final system frequency by changing FMPLL_SYNCR[RFD]
to its desired final value. Note that the FMPLL will not need to re-lock when only changing the
RFD, and that RFD must be programmed to be >1 to protect from overshoot.
5. Re-enable LOLIRQ.
NOTE
When using crystal reference mode or external reference mode, the
PREDIV value must not be set to any value that causes the phase/frequency
detector to go below 4 MHz. That is, the crystal or external clock frequency
divided by the PREDIV value must be in the range of 4 MHz – 20 MHz.
NOTE
MFD must be set such that the VCO stays within its valid range with the
selected predivider output.
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