MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-10 Freescale Semiconductor
12.2.1.10 Output Enable (OE)
OE is used to indicate when an external memory is permitted to drive back read data. External memories
must have their data output buffers off when OE is negated. OE is only asserted for chip select accesses.
OE
is driven by the EBI or an external master depending on who owns the external bus. For read cycles,
OE is asserted one clock after TS assertion and held until the termination of the transfer. For write cycles,
OE
is negated throughout the cycle.
The OE signal is shared with the calibration bus.
12.2.1.11 Read / Write (RD_WR)
RD_WR indicates whether the current transaction is a read access or a write access. The RD_WR signal
is shared with the calibration bus.
RD_WR is driven by the EBI or an external master depending on who owns the external bus. RD_WR is
driven in the same clock as the assertion of TS and valid address, and is kept valid until the cycle is
terminated.
12.2.1.12 Transfer Acknowledge (TA)
TA is asserted to indicate that the slave has received the data (and completed the access) for a write cycle,
or returned data for a read cycle. If the transaction is a burst read, TA is asserted for each one of the
transaction beats. For write transactions, TA is only asserted once at access completion, even if more than
one write data beat is transferred.
TA is driven by the EBI when the access is controlled by the chip selects or when an external master
initiated the transaction to an internal module. Otherwise, TA is driven by the slave device to which the
current transaction was addressed.
See Section 12.4.2.9, “Termination Signals Protocol” for more details.
12.2.1.13 Transfer Error Acknowledge (TEA)
In the 416-pin package of the MPC5553/MPC5554, TEA is asserted by either the EBI or an external device
to indicate that an error condition has occurred during the bus cycle. TEA assertion terminates the cycle
immediately, overriding the value of the TA signal.
TEA
is asserted by the EBI when the internal bus monitor detected a timeout error, or when an external
master initiated a transaction to an internal module and an internal error was detected.
The 324 BGA package of the MPC5553 has no TEA signal.
See Section 12.4.2.9, “Termination Signals Protocol” for more details.
12.2.1.14 Transfer Start (TS)
TS is asserted by the current bus owner to indicate the start of a transaction on the external bus. The TS
signal is shared with the calibration bus.
TS
is driven by the EBI or an external master depending on who owns the external bus. TS is only asserted
for the first clock cycle of the transaction, and is negated in the successive clock cycles until the end of the
transaction.
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