MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
18-4 Freescale Semiconductor
assigned to several channels, but a channel can only be associated with one function at a given moment.
The eTPU has the capability to change the function assigned to a channel if reconfigured by the
MPC5553/MPC5554 core. The association between functions and channels is defined by the
MPC5553/MPC5554 core.
The eTPU hardware supplies resource sharing features that support concurrency:
• A hardware scheduler dispatches the service request microengine routines based on a set of
priorities defined by the MPC5553/MPC5554’s core. Each channel has its own unique priority
assignment that primarily depends on CPU assignment. The channel’s number is an inherent
property also used to determine priority.
• A service request routine cannot be interrupted by another service request until it ends, that is, until
an end instruction is executed. This sequence of uninterrupted instruction execution is called a
thread. The core may terminate the thread by writing 1 to the FEND bit in the ETPU_ECR register.
• Channel-specific contexts (registers and flags) are automatically switched between the end of a
thread and the beginning of the next one.
• SDM arbitration, a dual-parameter coherency controller, and semaphores can be used to ensure
coherent access to eTPU data shared by both eTPU engines and the MPC5553/MPC5554 core.
18.1.3.1 eTPU Engine
The eTPU engine processes input pin transitions and generates output pin waveforms. These events are
triggered by eTPU timers (time bases) that are driven by a system clock to give absolute time control or
by an asynchronous counter such as an angle clock that may be tracking the angle of a rotating shaft.
Each eTPU engine consists of the following blocks: 32 independent timer channels, a task scheduler, a host
interface, and a microprocessor (hereinafter called a microengine) that has dedicated hardware for input
signal processing and output signal generation over the 32 I/O channels. Each channel can also choose
between two 24-bit counter registers for a time base.
The microengines fetch microinstructions from shared code memory (SCM). eTPU application parameters
and global and local variables, referred to as work data, are held in 32-bit shared data memory (SDM),
which is also used for passing information between the MPC5553/MPC5554’s core and both (or one)
microengines. The bus interface unit (BIU) allows the MPC5553/MPC5554’s core to access eTPU
registers, SDM, and SCM.
The blocks of an eTPU engine are duplicated in a dual eTPU configuration. eTPU engines A and B are
often referred to as eTPU A and eTPU B in this document.
18.1.3.1.1 Time Bases
Each eTPU engine has two 24-bit count registers TCR1 and TCR2 that provide reference time bases for
all match and input capture events. Prescalers for both time bases are controlled by the
MPC5553/MPC5554 core through bit fields in the eTPU engine configuration registers.
The values for each of TCR1 and TCR2 counter registers can be independently derived from the system
clock or from an external input via the TCRCLK pin. In addition, the TCR2 time base can be derived from
special angle-clock hardware that enables implementing angle-based functions. This feature is added to
support advanced angle-based engine control applications.
The TCRs may also drive an eMIOS time base through the shared time and counter (STAC) bus, or they
may be written by eTPU function software.
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