Freescale Semiconductor MPC5553 - Page 800

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 19-45
Figure 19-24. Command Flow During eQADC Operation
Figure 19-25. Result Flow During eQADC Operation
Command
Queue
System
Memory
CFIFO n
ADC
Priority
Command
Buffer
(32-bits)
(32-bits)
FIFO
Control
Unit
To
ADCs
eQADC SSI
eQADC
ADC
eQADC SSI
External Device
Logic
&
Buffers
DMA
Transaction
Done Signals
Host CPU
or
DMAC
DMA
or Interrupt
Requests
NOTES:
n = 0, 1, 2, 3, 4, 5
ADC Command
CFIFO Header
Command
Message
Result
Queue
System
Memory
RFIFO n
ADC
Decoder
(16-bits)
(16-bits)
FIFO
Control
Unit
eQADC SSI
eQADC
ADC
eQADC SSI
External Device
Logic
&
Buffers
DMA
Transaction
Done Signals
Host CPU
or
DMAC
DMA
or Interrupt
Requests
NOTES:
n = 0, 1, 2, 3, 4, 5
ADC Result
RFIFO Header
Result
Message
Result
Format
&
Calibration
Submodule