MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
21-22 Freescale Semiconductor
21.4.4.1 Transmitter Character Length
The eSCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in eSCI
control register 1 (ESCIx_CR1) determines the length of data characters. When transmitting 9-bit data, bit
T8 in the eSCI data register (ESCIx_DR) is the ninth bit (bit 8).
21.4.4.2 Character Transmission
To transmit data, the MCU writes the data bits to the eSCI data register (ESCIx_DR), which in turn are
transferred to the transmit shift register. The transmit shift register then shifts a frame out through the TXD
signal, after it has prefaced them with a start bit and appended them with a stop bit. The eSCI data register
(ESCIx_DR) is the buffer (write-only during transmit) between the internal data bus and the transmit shift
register.
The eSCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from
the buffer (ESCIx_DR) to the transmit shift register. The transmit driver routine may respond to this flag
by writing another byte to the transmitter buffer (ESCIx_DR), while the shift register is still shifting out
the first byte.
To initiate an eSCI transmission:
1. Configure the eSCI:
a) Turn on the module by clearing ESCIx_CR2[MDIS] if this bit is set.
b) Select a baud rate. Write this value to the eSCI control register 1 (ESCIx_CR1) to start the
baud rate generator. Remember that the baud rate generator is disabled when the
ESCIx_CR1[SBR] field is zero. When using 8-bit writes, writes to the ESCIx_CR1[0–7] have
no effect without also writing to ESCIx_CR1[8–15].
c) Write to ESCIx_CR1 to configure word length, parity, and other configuration bits (LOOPS,
RSRC, M, WAKE, ILT, PE, PT).
d) Enable the transmitter, interrupts, receive, and wake-up as required, by writing to the
ESCIx_CR1 register bits (TIE, TCIE, RIE, ILIE, TE, RE, RWU, SBK). A preamble or idle
character will now be shifted out of the transmitter shift register.
NOTE
A single 32-bit write to ESCI_CR1 may be used in place of steps b–d above.
2. Transmit procedure for each byte:
a) Poll the TDRE flag by reading the ESCIx_SR or responding to the TDRE interrupt. Keep in
mind that the TDRE bit resets to 1.
b) If the TDRE flag is set, write the data to be transmitted to ESCIx_DR, where the ninth bit is
written to the T8 bit in ESCIx_DR if the eSCI is in 9-bit data format. A new transmission will
not result until the TDRE flag has been cleared.
3. Repeat step 2 for each subsequent transmission.
NOTE
The TDRE flag is set when the shift register is loaded with the next data to
be transmitted from ESCIx_DR, which occurs approximately half-way
through the stop bit of the previous frame. Specifically, this transfer occurs
9/16ths of a bit time AFTER the start of the stop bit of the previous frame.
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