GARD 8000 SYS RFL Electronics
November 28, 2017 x (973) 334-3100
Figure 7-69. Output Mapping web page (Typical)...........................................................................................................................7-110
Figure 7-70. System Logic Configuration web page .......................................................................................................................7-111
Figure 7-71. Option Settings web page (Typical) ............................................................................................................................7-112
Figure 7-72. System Logic Configuration web page .......................................................................................................................7-113
Figure 7-73. Timer Settings web page (Typical) ..............................................................................................................................7-114
Figure 8-1. Two input AND gate ............................................................................................................................................................8-1
Figure 8-2. Three input AND gate ..........................................................................................................................................................8-2
Figure 8-3. Two Input OR gate................................................................................................................................................................8-2
Figure 8-4. Three Input OR gate .............................................................................................................................................................8-3
Figure 8-5. XOR gate ................................................................................................................................................................................8-3
Figure 8-6. Inverter gate............................................................................................................................................................................8-4
Figure 8-7. Latch ........................................................................................................................................................................................8-5
Figure 8-8. Toggle Gate ............................................................................................................................................................................8-6
Figure 8-9. Timer .......................................................................................................................................................................................8-7
Figure 8-10. Buffer ....................................................................................................................................................................................8-8
Figure 8-11. System Logic Configuration web page .........................................................................................................................8-10
Figure 8-12. Input Mapping web page .................................................................................................................................................8-11
Figure 8-13. Output Mapping web page ..............................................................................................................................................8-12
Figure 8-14. Option Settings web page ................................................................................................................................................8-13
Figure 8-15. System Timer Setting web page .....................................................................................................................................8-14
Figure 9-1. Permissive Underreaching Transfer Trip ..........................................................................................................................9-2
Figure 9-2. Permissive Overerreaching Transfer Trip .........................................................................................................................9-2
Figure 9-3. Direct Transfer Trip ..............................................................................................................................................................9-3
Figure 9-4. Directional Comparison Blocking ......................................................................................................................................9-4
Figure 9-5. Directional Comparison Unblocking .................................................................................................................................9-5
Figure 10-1. GARD 8000 PLC FSK Block Diagram ........................................................................................................................10-4
Figure 10-2. Minimum Channel Spacing (FSK).................................................................................................................................10-5
Figure 10-3. GARD 8000 PLC On/Off Block Diagram....................................................................................................................10-8
Figure 10-4. GARD PLC Analog Module Carrier Frequency Range Jumper Settings .............................................................10-10
Figure 10-5. PLC Analog Module, Carrier Level Indicator Modes - Jumpers............................................................................10-16
Figure 10-6. CLI Meter, Front Panel Mounting on 3U Chassis.....................................................................................................10-17
Figure 10-7. PLC Digital Module (500455-1) ..................................................................................................................................10-18
Figure 10-8. 9508 RF Chassis Mounted on the GARD 8000.........................................................................................................10-19
Figure 10-9. Front View of the 9508 RF Chassis showing Module locations.............................................................................10-20
Figure 10-10. 9508 RF Chassis Block Diagram ...............................................................................................................................10-21
Figure 10-11. 9508 RF Chassis Power Amplifier ............................................................................................................................10-21
Figure 10-12. 9508 RF Chassis Power Amplifier, Power Supply .................................................................................................10-22
Figure 10-13. 9508 RF Chassis Power Amplifier, Power Supply .................................................................................................10-22
Figure 10-14. TX Filter, Top View .....................................................................................................................................................10-23
Figure 10-15. Balance Board ...............................................................................................................................................................10-24
Figure 10-16. Line Board......................................................................................................................................................................10-25
Figure 10-17. Block Diagram, RFL 9508 Line Board.....................................................................................................................10-25
Figure 10-18. RFL 9508 RX Filter Board..........................................................................................................................................10-27
Figure 10-19. RFL 9508 RX Connection Board...............................................................................................................................10-28
Figure 10-20. RFL 9508 Attenuator Board .......................................................................................................................................10-28
Figure 10-21. RFL 9508 RF Mother Board, Rear View .................................................................................................................10-29
Figure 10-22. Module Placement in a Typical 50W 9508 RF Chassis (Top View) ...................................................................10-31
Figure 10-23. Cable Connections in the RF Chassis........................................................................................................................10-33
Figure 10-24. Module Placement in the Auxiliary 3U Chassis for the 100W System...............................................................10-34
Figure 10-25. Location of 50W Power Amplifier Module .............................................................................................................10-35
Figure 10-26. Circuit Board, 50W Power Amp showing locations of jumpers, switches, connectors, potentiometers.......10-35
Figure 10-27. Location of jumpers on the Tx Filter, PC Board 107828-2 ...................................................................................10-38
Figure 10-28. Location of jumpers on the Tx Filter, PC Board 107828-1 ...................................................................................10-40
Figure 10-29. Location of jumpers on the Balance Board ..............................................................................................................10-41
Figure 10-30. Location of jumpers on the Line Board ....................................................................................................................10-42
Figure 10-31. Attenuator Board, Location of SW1 ..........................................................................................................................10-44
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