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RFL Electronics GARD 8000 - Figure 10-36. Default Logic, GA RD 8000 On-Off PLC

RFL Electronics GARD 8000
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Power Line Carrier
GARD 8000 SYS RFL Electronics
November 7, 2011 10-55 (10-56 blank) 973-334.3100
FALSE
TRIG13
TRIG14
TRIG16
TRIG17
TRIG18
TRIG19
TRIG15
TRIG12
2
2
2
2
2
2
2
2
BUF
BUF
BUF
BUF
BUF
BUF
BUF
BUF
1
1
1
1
1
1
1
1
CHECKBACK_TEST_FAIL_1
CHECKBACK_TEST_FAIL_2
CHECKBACK_TEST_FAIL_3
CHECKBACK_TEST_FAIL_4
CHECKBACK_TEST_FAIL_5
CHECKBACK_TEST_FAIL_6
CHECKBACK_TEST_FAIL_7
CHECKBACK_TEST_FAIL_8
Start Carrier
Stop Carrier
Stop AND/OR
Setting
START1
COUNTER_4
COUNTER_5
COUNTER_6
TB2-1
TB2-2
TB2-3
TB2-4
TB2-5
TB2-6
TB2-7
TB2-8
TB2-9
TB2-10
TB2-11
TB2-12
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
REMOTE INITIATE
RESERVE KEY
COUNTER_1
COUNTER_2
6 Input
Slot N* Lower
MODULE2
LOGIC BITS
106 - 111
BLOCK RX
BLOCK RX
BLOCK RX
BLOCK RX
CHECKBACK TEST IN PROGRESS
CHECKBACK TEST FAILED
COUNTER_3
PLC_MODULE1
PLC_MODULE1
TRIG9
BLOCK_1
BLOCK_2
BLOCK_3
BLOCK_4
1
2
1
2
1
2
1
2
TX_FAIL_DETECTED
1
2
3
REFLECTED_POWER_ALARM
HMIIN2
AND2
ENABLE_RPM_ALARM
1
2
3
AND2
2
2
IN
IN
TIMER
NUMBER=1
ATT_DEC=50_50
TIMER
NUMBER=2
ATT_DEC=50_50
BUF
BUF
BUF
BUF
BLOCK_RX_1
BLOCK_RX_2
BLOCK_RX_3
BLOCK_RX_4
OUTPUT MAPPING
Output 1
LOGIC BITS 112-117
6 RELAY OUTLETS
SLOT N* LOWER
TB2-13
TB2-14
TB2-15
TB2-16
TB2-17
TB2-18
TB2-19
TB2-20
TB2-21
TB2-22
TB2-23
TB2-24
MODULE1
Output 2
Output 3
Output 4
Output 5
Output 6
OUT
OUT
1
2
1
1
BUF
1
2
BUF
TRIG8
1
2
BUF
1
2
BUF
CHECKBACK_FAILED
CHECKBACK_TIP
1
2
1
2
BUF
BUF
1
2
1
2
3
AND2
1
2
TRIG10
1
2
1
2
TRIG20
TRIG11
NOT
BUF
BUF
CHECKBACK_TRIP
CHECKBACK_FAILED
REFLECTED_PWR_ALARM
TX_FAIL
Output 1
6 RELAY OUTLETS
SLOT M* LOWER
TB2-13
TB2-14
TB2-15
TB2-16
TB2-17
TB2-18
TB2-19
TB2-20
TB2-21
TB2-22
TB2-23
TB2-24
MODULE3
LOGIC BITS 9-14
Output 2
Output 3
Output 4
Output 5
Output 6
Output 7
Output 8
Output 9
Output 10
Output 11
Output 12
Transmit into Logic BUS >>>>>>>
Receive from Logic BUS >>>>>>>
Logic (6 bits)
6 Input (6 bits) PLC On/Off (17 bits)
Logic Bus Assignment
PLC On/Off (12 bits)
6 Output (6 bits)
Logic (17 bits)
Bit 100
Bit 106
Bit 112
Bit 118
Bit 128
IOOUTS11
1
2
BUF
1
2
BUF
TRUE
FALSE
IOOUTS10
Start AND/OR
Setting
START2
Start 1
Invert
Setting
Start 2
Invert
Setting
STOP1
Stop 1
Invert
Setting
STOP2
Stop 2
Invert
Setting
* Subject to chassis location.
Overview On-Off
Logic Bus Bits RX 100-111, TX 112-128
Figure 10-36. Default Logic, GARD 8000 On-Off PLC
For reference ONLY.
See specific drawings provided with your order.

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