RFL Electronics GARD 8000 - 8.3 LOGIC CONFIGURATION

System Logic
GARD 8000 SYS RFL Electronics
March 26, 2008 8-9 973.334.3100
8.3 LOGIC CONFIGURATION
The following scheme has been implemented for default logic and programmable logic in general.
Custom designs are generated at RFL that include a logic schematic created in ORCAD and a logic
setting database. These two files are to be downloaded to the unit.
Once these files are downloaded, the GARD will automatically generate user friendly web pages for
changing the configuration of the logic. The logic is field programmable to the following extent.
Timer Settings - All of the timer settings are displayed with custom labels. Attack and decay times
can be entered into text boxes. Timers with fixed values are not be displayed in the user settings.
Option Setting – The system designer (RFL systems engineering) is free to put in as much
programmability as desired in the logic. Different operating modes can be selected, inversions, etc.
Any modification of the logic operating modes must be added in by the designer. These controls are
present on the Option Setting web page with radio buttons for controls.
I/O Mapping – The inputs and outputs that are planned for the chassis are included in the logic design.
The mapping of inputs to logic and logic to outputs can be done in the field. The available logic inputs
are shown on the web pages and the possible inputs to drive them can be selected from a pull down
list. The available hardware outputs will be shown and the possible logic points to drive them can be
selected from a pull down list.