RFL Electronics GARD 8000 - Page 15

GARD 8000 SYS RFL Electronics
November 28, 2017 xv (973) 334-3100
Table 8-12. Output Mapping ..................................................................................................................................................................8-18
Table 8-13. Option Settings....................................................................................................................................................................8-19
Table 8-14. Default Logic Timers .........................................................................................................................................................8-20
Table 8-15. HMI Bit Assignment ..........................................................................................................................................................8-21
Table 8-16. SOE Triggers Bit Assignment.........................................................................................................................................8-21
Table 8-17. Logic Bit Assignment .......................................................................................................................................................8-22
Table 8-18. Metering Module Bit Placement on the Logic Bus .....................................................................................................8-23
Table 10-1. 2F Trip Transport Delay and Channel Spacing ............................................................................................................10-6
Table 10-2. 3F Trip Transport Delay and Channel Spacing ............................................................................................................10-6
Table 10-3. On/Off Block Transport Delay and Channel Spacing ..................................................................................................10-9
Table 10-4. PLC Analog Module Assembly Part Numbers (part number series 500935) ........................................................10-10
Table 10-5. TX Filter Jumper settings (part number series 500935) ............................................................................................10-11
Table 10-6. PLC Analog Module Assembly Part Numbers (part number series 500930) ........................................................10-11
Table 10-7. TX Filter Jumper settings part number series 500930 ...............................................................................................10-12
Table 10-8. Common RPM test values...............................................................................................................................................10-15
Table 10-9. Carrier Level Indicator loads ..........................................................................................................................................10-16
Table 10-10. Modules included in the 9508 RF Chassis.................................................................................................................10-20
Table 10-11. Motherboard Rear Panel Connector Assignments....................................................................................................10-29
Table 10-12. TB-1 Terminal Assignments ........................................................................................................................................10-30
Table 10-13. Module Placement in the RF Chassis (50W System) ..............................................................................................10-31
Table 10-14. RF Chassis Cables..........................................................................................................................................................10-33
Table 10-15. RF Analog Chassis Jumper Configurations and other Settings..............................................................................10-34
Table 10-16. Function of jumpers, connectors and potentiometers on Power Amp...................................................................10-36
Table 10-17. Function of DIP Switches SW1 and SW2 on Power Amp Board..........................................................................10-37
Table 10-18. Tx Filter Setup Jumpers ................................................................................................................................................10-39
Table 10-19. Setting Jumpers on the Balance Board .......................................................................................................................10-41
Table 10-20. Line Board, Setup Jumpers and Switch Settings ......................................................................................................10-43
Table 12-1. Audio Tone Logic Block Diagrams ................................................................................................................................12-1
Table 13-1 LED Functions on Front Current Diff. Board ...............................................................................................................13-3
Table 13-2 Maximum Number of Oscillography Records ............................................................................................................13-79