DocID024597 Rev 5 7/1830
RM0351 Contents
48
6.4.12 AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 240
6.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 240
6.4.14 APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 243
6.4.15 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 244
6.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 245
6.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 247
6.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 248
6.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 249
6.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 252
6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 254
6.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
6.4.26 APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.4.28 Peripherals independent clock configuration register (RCC_CCIPR) . 265
6.4.29 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 268
6.4.30 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
6.4.31 Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 272
6.4.32 Peripherals independent clock configuration register (RCC_CCIPR2) 273
6.4.33 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
7 Clock recovery system (CRS) (only valid for STM32L496xx/4A6xx
devices) 279
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
7.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
7.3 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
7.3.1 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
7.3.2 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
7.3.3 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.3.4 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 282
7.3.5 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
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