MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 22-17
22.3.3.4.2 RX 14 Mask (CANx_RX14MASK)
The CANx_RX14MASK register has the same structure as the RX global mask register and is used to
mask message buffer 14. Access to this register is unrestricted. Note that CANx_RX14MASK is
unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
• Address offset: 0x14
• Reset value: 0x1FFF_FFFF
22.3.3.4.3 RX 15 Mask (CANx_RX15MASK)
The CANx_RX15MASK register has the same structure as the RX global mask register and is used to
mask message buffer 15. Access to this register is unrestricted. Note that CANx_RX15MASK is
unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).
• Address offset: 0x18
• Reset value: 0x1FFF_FFFF
22.3.3.5 Error Counter Register (CANx_ECR)
CANx_ECR has two 8-bit fields reflecting the value of two FlexCAN2 error counters: the transmit error
counter (TXECTR field) and receive error counter (RXECTR field). The rules for increasing and
decreasing these counters are described in the CAN protocol and are completely implemented in the
FlexCAN2 module. Both counters are read only except in freeze mode, where they can be written by the
CPU.
Writing to the CANx_ECR while in freeze mode is an indirect operation. The data is first written to an
auxiliary register and then an internal request/acknowledge procedure across clock domains is executed.
All this is transparent to the user, except for the fact that the data will take some time to be actually written
to the register. If desired, software can poll the register to discover when the data was actually written.
FlexCAN2 responds to any bus state as described in the protocol: transmitting, for example, an ‘error
active’ or ‘error passive’ flag, delaying its transmission start time (‘error passive’), and avoiding any
influence on the bus when in the bus off state. The following are the basic rules for FlexCAN2 bus state
transitions:
• If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the CANx_ESR is updated to reflect the ‘error passive’ state.
• If the FlexCAN2 state is ‘error passive,’ and either TXECTR or RXECTR decrements to a value
less than or equal to 127 while the other already satisfies this condition, the FLTCONF field in the
CANx_ESR is updated to reflect the ‘error active’ state.
• If the value of TXECTR increases to be greater than 255, the FLTCONF field in the CANx_ESR
is updated to reflect the bus off state, and an interrupt may be issued. The value of TXECTR is then
reset to zero.
• If FlexCAN2 is in the bus off state, then TXECTR is cascaded together with another internal
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
TXECTR is reset to zero and counts in a manner where the internal counter counts 11 such bits and
then wraps around while incrementing the TXECTR. When TXECTR reaches the value of 128, the
FLTCONF field in CANx_ESR is updated to be ‘error active’ and both error counters are reset to
zero. At any instance of dominant bit following a stream of less than 11 consecutive recessive bits,
the internal counter resets itself to zero without affecting the TXECTR value.
• If during system start-up, only one node is operating, then its TXECTR increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by the ACKERR bit in
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