Freescale Semiconductor MPC5553 - Page 1073

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-34 Freescale Semiconductor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ROPCMCK_DIV EOC 0PTMWEN00000000
W
Reset0000000000000000
Nexus Reg 0x2
1514131211109876543210
R00000000 OVC EIC TM
W
Reset0000000000000000
Nexus Reg 0x2
Figure 25-13. Development Control Register 1 (DC1)
Table 25-25. DC1 Field Descriptions
Bits Name Description
31 OPC
1
Output port mode control.
0 Reduced-port mode configuration (4 MDO pins)
1 Full-port mode configuration (12 MDO pins)
30–29 MCK_DIV
[1:0]
1
MCKO clock divide ratio.
00 MCKO is 1x processor clock freq.
01 MCKO is 1/2x processor clock freq.
10 MCKO is 1/4x processor clock freq.
11 MCKO is 1/8x processor clock freq.
28–27 EOC
[1:0]
EVTO control.
00 EVTO upon occurrence of watchpoints (configured in DC2)
01 EVTO upon entry into debug mode
10 EVTO upon timestamping event
11 Reserved
26 — Reserved.
25 PTM Program trace method.
0 Program trace uses traditional branch messages
1 Program trace uses branch history messages
24 WEN Watchpoint trace enable.
0 Watchpoint Messaging disabled
1 Watchpoint Messaging enabled
23–8 — Reserved.
7–5 OVC
[2:0]
Overrun control.
000 Generate overrun messages
001–010 mReserved
011 Delay processor for BTM / DTM / OTM overruns
1XX Reserved