MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
5-8 Freescale Semiconductor
Each OPACR contains up to eight of these module-access fields, and the OPACR register structure is
shown in Table 5-2 and Table 5-3.
The OPACR registers with their access fields are shown in Figure 5-4. Seven OPACR registers are used,
three for bridge A, and four for bridge B.
NOTE
Not all members of the MPC5500 family have PBRIDGE_x_PACR and
PBRIDGE_x_OPACR. On the parts that do not have them, writes to their
addresses will receive a transfer error. If ensuring code compatibility across
all family members is wanted, then writes to those addresses must be
qualified with SIU_MIDR[PARTNUM].
NOTE
PBRIDGE_x_PACR and PBRIDGE_x_OPACR should be written with a
read/modify/write for code compatibility.
The type of peripheral designated by each PACR and OPACR access field is shown in Table 5-6.
012 3 456789101112131415
RBW0
1
SP0 WP0 TP0 BW1 SP1 WP1 TP1 BW2 SP2 WP2 TP2 BW3 SP3 WP3 TP3
W
Reset
A_PACR0
01
2
01
2
000000000000
Reset
B_PACR0
01
2
01
2
01
2
0000000000
Reset
B_PACR2
01
2
0001
2
0001
2
0001
2
00
Reg Addr Base + 0x0020 (PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0); Base + 0x0028 (PBRIDGE_B_PACR2)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R BW4 SP4 WP4 TP4 BW5 SP5 WP5 TP5 BW6 SP6 WP6 TP6 BW7 SP7 WP7 TP7
W
Reset
A_PACR0
000 0 000000000000
Reset
B_PACR0
000 0 000000000000
Reset
B_PACR2
000 0 000000000000
Reg Addr Base + 0x0020 (PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0); Base + 0x0028 (PBRIDGE_B_PACR2)
Figure 5-3. Peripheral Access Control Registers (PBRIDGE_x_PACRn)
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