Freescale Semiconductor MPC5553 - Page 194

System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 6-15
6.3.1.6 DMA/Interrupt Request Select Register (SIU_DIRSR)
The SIU_DIRSR allows selection between a DMA or interrupt request for events on the IRQ[0]–IRQ[3]
inputs. The SIU_DIRSR selects between DMA and interrupt requests. If the corresponding bits are set in
SIU_EISR and the SIU_DIRER, then the DMA/interrupt request select bit determines whether a DMA or
interrupt request is asserted.
Address: Base + 0x0018 Access: Read / Write[16:31]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0000000000000000
W
Reset
0000000000000000
Address: Base + 0x0018 Access: Read / Write[16:31]
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EIRE15 EIRE14 EIRE13 EIRE12 EIRE11 EIRE10 EIRE9 EIRE8 EIRE7 EIRE6 EIRE5 EIRE4 EIRE3 EIRE2 EIRE1 EIRE0
W
Reset
0000000000000000
Figure 6-7. SIU DMA/Interrupt Request Enable Register (SIU_DIRER)
Table 6-9. SIU_DIRER Field Descriptions
Register Bit Range
Field Name
Function
0–15
Reserved.
16–31
EIREn
External interrupt request enable n. Enables the assertion of the interrupt request from the
SIU to the interrupt controller when an edge-triggered event occurs on the IRQ
[n] pin.
0 External interrupt request is disabled.
1 External interrupt request is enabled.
Address: Base + 0x001C Access: Read / Write[28:31]
0123456789101112 13 14 15
R
000000000000 0000
W
Reset
0 00000000000 0000
Address: Base + 0x001C Access: Read / Write[28:31]
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
000000000000
DIRS3 DIRS2 DIRS1 DIRS0
W
Reset
000000000000 0000
Figure 6-8. DMA/Interrupt Request Select Register (SIU_DIRSR)