System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 6-95
6.3.1.16 External IRQ Input Select Register (SIU_EIISR)
The SIU_EIISR selects the source for the external interrupt/DMA inputs.
4–5
TSEL3
eQADC trigger input select 3. Specifies the input for eQADC trigger 3.
00 GPIO[207]
01 ETPUA[28] channel
10 EMIOS[14] channel
11 ETRIG[1] pin
6–7
TSEL2
eQADC trigger input select 2. Specifies the input for eQADC trigger 2
00 GPIO[206]
01 ETPUA[29] channel
10 EMIOS[15] channel
11 ETRIG[0] pin
8–9
TSEL1
eQADC trigger input select 1. Specifies the input for eQADC trigger 1
00 GPIO[207]
01 ETPUA[31] channel
10 EMIOS[11] channel
11 ETRIG[1] pin
10–11
TSEL0
eQADC trigger input select 0. Specifies the input for eQADC trigger 0
00 GPIO[206]
01 ETPUA[30] channel
10 EMIOS[10] channel
11 ETRIG[0] pin
12–31
Reserved.
Address: Base + 0x0904 Access: Read / write[0:31]
0123456789101112131415
R
ESEL15 ESEL14 ESEL13 ESEL12 ESEL11 ESEL10 ESEL9 ESEL8
W
Reset
0000000000000000
Address: Base + 0x0904 Access: Read / write[0:31]
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESEL7 ESEL6 ESEL5 ESEL4 ESEL3 ESEL2 ESEL1 ESEL0
W
Reset
0000000000000000
Figure 6-132. External IRQ Input Select Register 1 (SIU_EIISR)
Table 6-48. SIU_ETISR Field Descriptions
Register Bit Range
Field Name
Description