MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 8-13
8.2.1.14 RAM ECC Data High Register (ECSM_REDRH)
The ECSM_REDRH and ECSM_REDRL are 32-bit registers for capturing the data associated with the
last, properly-enabled ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an
ECC event in the RAM causes the address, attributes and data associated with the access to be loaded into
the ECSM_REAR, ECSM_REMR, ECSM_REAT, and ECSM_REDRH and ECSM_REDRL, and the
appropriate flag (RFNCE) in the ECSM_ESR to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
Table 8-13. ECSM_REAT Field Descriptions
Bits Name Description
0 WRITE Write. The reset value of this field is undefined.
0 System bus read access
1 System bus write access
1–3 SIZE
[0:2]
Size. The reset value of this field is undefined.
000 8-bit system bus access
001 16-bit system bus access
010 32-bit system bus access
011 64-bit system bus access
1xx Reserved
4 PROT0 Protection: cache. The reset value of this field is undefined.
0 Non-cacheable
1 Cacheable
5 PROT1 Protection: buffer. The reset value of this field is undefined.
0 Non-bufferable
1Bufferable
6 PROT2 Protection: mode. The reset value of this field is undefined.
0 User mode
1 Supervisor mode
7 PROT3 Protection: type. The reset value of this field is undefined.
0I-Fetch
1Data
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