MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
8-14 Freescale Semiconductor
8.2.1.15 RAM ECC Data Low Registers (ECSM_REDRL)
The ECSM_REDRH and ECSM_REDRL are 32-bit registers for capturing the data associated with the
last, properly-enabled ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an
ECC event in the RAM causes the address, attributes and data associated with the access to be loaded into
the ECSM_REAR, ECSM_REMR, ECSM_REAT, ECSM_REDRH, and ECSM_REDRL, and the
appropriate flag (RFNCE) in the ECSM_ESR to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
0123456789101112131415
RREDH
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 0x0068
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RREDH
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 0x0068
1
“U” signifies a bit that is uninitialized.
Figure 8-12. RAM ECC Data High Register (ECSM_REDRH)
Table 8-14. ECSM_REDRH Field Descriptions
Bits Name Description
0–31 REDH
[0:31]
RAM ECC data. Contains the data associated with the faulting access of the last,
properly-enabled RAM ECC event. The register contains the data value taken directly from
the data bus. The reset value of this field is undefined.
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