Freescale Semiconductor MPC5553 - Page 337

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
9-18 Freescale Semiconductor
9.3.1.10 eDMA Clear Error Register (EDMA_CER)
The EDMA_CER provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERH
or EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the EDMA_ERH or EDMA_ERL to be cleared. Setting bit 1 (CERRn)
provides a global clear function, forcing the entire contents of the EDMA_ERH and EDMA_ERL to be
zeroed, clearing all channel error indicators. Reads of this register return all zeroes. For the MPC5553, bit
2 (CERR1) is not used.
9.3.1.11 eDMA Set START Bit Register (EDMA_SSBR)
The EDMA_SSBR provides a simple memory-mapped mechanism to set the START bit in the TCD of the
given channel. The data value on a register write causes the START bit in the corresponding transfer
control descriptor to be set. Setting bit 1 (SSBn) provides a global set function, forcing all START bits to
be set. Reads of this register return all zeroes. For the MPC5553, bit 2 (SSB1) is not used.
Table 9-10. EDMA_CIRQR Field Descriptions
Bits Name Description
0 — Reserved.
1–7 CINT
[0:6]
Clear interrupt request.
0–63 Clear the corresponding bit in EDMA_IRQRH or EDMA_IRQRL
64–127 Clear all bits in EDMA_IRQRH or EDMA_IRQRL
Note: For the MPC5553, the value 32-63 [bit 2 (CINT1)] is reserved.
01234567
R00000000
W CERR[0:6]
Reset00000000
Reg Addr Base + 0X001D
Figure 9-13. eDMA Clear Error Register (EDMA_CER)
Table 9-11. EDMA_CER Field Descriptions
Bits Name Description
0 — Reserved.
1–7 CERR
[0:6]
Clear error indicator.
0–63 Clear corresponding bit in EDMA_ERH or EDMA_ERL
64–127 Clear all bits in EDMA_ERH and EDMA_ERL
Note: For the MPC5553, the value 32-63 [bit 2 (CERR1)] is reserved.