MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
11-14 Freescale Semiconductor
4–8 MFD
[0:4]
Multiplication factor divider. The MFD bits control the value of the divider in the FMPLL
feedback loop. The value specified by the MFD bits establish the multiplication factor
applied to the reference frequency. The decimal equivalent of the MFD binary number is
substituted into the equation from Table 11-10 for F
sys
to determine the equivalent
multiplication factor.
When the MFD bits are changed, the FMPLL loses lock. At this point, if modulation is
enabled, the calibration sequence is reinitialized. To prevent an immediate reset, the
LOLRE bit must be cleared before writing the MFD bits. In dual-controller mode, the MFD
bits are ignored and the multiplication factor is equivalent to 2X. In bypass mode the MFD
bits have no effect.
Note: Programming an MFD value such that the ICO operates outside its specified range
will cause unpredictable results and the FMPLL will not lock. Refer to the MPC5553
Microcontroller Data Sheet and MPC5554 Microcontroller Data Sheet for details on the
ICO range.
Note: To avoid unintentional interrupt requests, disable LOLIRQ before changing MFD
and then reenable it after acquiring lock.
9 — Reserved.
10–12 RFD
[0:2]
Reduced frequency divider. The RFD bits control a divider at the output of the FMPLL. The
value specified by the RFD bits establish the divisor applied to the FMPLL frequency.
Changing the RFD bits does not affect the FMPLL; hence, no re-lock delay is incurred.
Resulting changes in clock frequency are synchronized to the next falling edge of the
current system clock. However these bits must only be written when the lock bit (LOCK) is
set, to avoid exceeding the allowable system operating frequency. In bypass mode, the
RFD bits have no effect.
13 LOCEN Loss-of-clock enable. The LOCEN bit determines whether the loss of clock function is
operational. See Section 11.4.2.6, “Loss-of-Clock Detection” and Section 11.4.2.6.1,
“Alternate/Backup Clock Selection” for more information.
In bypass mode, this bit has no effect.
LOCEN does not affect the loss of lock circuitry.
0 Loss of clock disabled.
1 Loss of clock enabled.
Table 11-5. FMPLL_SYNCR Field Descriptions (Continued)
Bits Name Description
RFD[0:2] Output Clock Divide Ratio
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
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