MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
1-24 Freescale Semiconductor
Table 1-5 shows the memory map for the MPC5553 and MPC5554 family MCU configured as a master
in multi-master system with another MPC5500 family MCU acting as the slave.
0xC0_0000–0xC0_FFFF 64 Kbytes Slave Internal SRAM
0xC1_0000–0xCF_FFFF (1 Mbytes–64 Kbytes) Reserved
0xD0_0000–0xDF_FFFF 1 Mbytes Reserved
0xE0_0000–0xEF_FFFF 1 Mbytes Slave Bridge A Peripherals
0xF0_0000–0xFF_FFFF 1 Mbytes Slave Bridge B Peripherals
1
Only the lower 24 address signals (addr[8:31]) are available off-chip.
2
This address range is not part of the MPC5500 family slave memory map, rather it is shown to illustrate the addressing scheme
for off-chip accesses in multi-master mode.
3
The shadow row of the slave FLASH is not accessible by an external master.
Table 1-5. MPC5500 Family Master Memory Map (Multi Master Mode)
Base Address Size (bytes) Use
On-Chip
0x0000_0000 2 Mbytes(MPC55545)
1.5 Mbytes(MPC5553)
Flash array
0x0020_0000
0x0018_0000
(14 Mbytes–1024 bytes)
(14.5 Mbytes – 1024 bytes)
Reserved
0x00FF_FC00 1024 Flash shadow row
0x0100_0000 496 Mbytes Emulation mapping flash
Off-Chip
0x2000_0000 8 Mbytes
1
External memory
0x2080_0000 2 Mbytes Slave Flash
0x20A0_0000
0x2098_0000
2 Mbytes Reserved
Not Addressable 1024 Slave flash shadow row
0x20C0_0000 64 Kbytes Slave internal SRAM
0x20C1_0000 (2 Mbytes–64 Kbytes) Reserved
0x20E0_0000 1 Mbytes Slave bridge A peripherals
0x20F0_0000 1 Mbytes Slave bridge B peripherals
On-Chip
0x4000_0000 64 Kbytes Internal SRAM
0x4001_0000 (2048 Mbytes–64 Kbytes) Reserved
0xC000_0000 63 Mbytes Reserved
Table 1-4. MPC5500 Family Slave Memory Map as Seen from an External Master (Continued)
External Address Range
1
Size (bytes) Use
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