MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 12-51
12
IRP is ignored (treated as 1) in the MCU_WAIT state because the EBI does not optimally support an internal master
cancelling its bus request. If IRP is negated in this state, the EBI still grants the internal master the bus as if IRP was still
asserted, and a few cycles may be wasted before the external master may be able to grab the bus again (depending on
BR
, BB, etc., according to normal transition logic).
13
The default BB output is 0 for this state. However, anytime the EBI transitions from a state where BB = 0 to a state where
BB
= hiZ, there is one external cycle (in this state) where the EBI drives BB = 1 to actively negate the pin before letting
go to hiZ. In the case where a second granted internal request (IRP = 1, ETP=1) is ready to start just before the transition
to the hiZ state would otherwise have occurred (during the BB
= 1active negate cycle), then BB is driven back to 0 to
start the next access without ever leaving this state or going to hiZ.
14
BR is ignored (treated as 0) in the EXT_WAIT state because the EBI does not optimally support an external master
cancelling its bus request. If BR is negated in this state, the EBI still grants the external master the bus as if BR was still
asserted, and a few cycles may be wasted while the external master ‘window-of-opportunity’ is satisfied before the
internal master may be able to grab the bus again (depending on BR
, BB, etc., according to normal transition logic).
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