Freescale Semiconductor MPC5553 - Page 515

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-66 Freescale Semiconductor
Figure 12-48. External Master 32-bit Read from MCU with DBM=1
Figure 12-49. External Master 32-bit Write to MCU with DBM=1
Receive bus grant and bus busy
negated for 2nd cycle
Assert BB drive address
and assert TS
Using the internal arbiter
CLKOUT
BR (Input)
RD_WR
TSIZ[0:1]
BDIP
BG
BB
ADDR[8:31]
DATA[0:15]
TS
(Input)
Minimum
2 wait states
DATA is valid
TA
(Output)
‘00’
DATA is valid
DATA is valid
Receive bus grant and bus busy
negated for 2nd cycle
Assert BB drive address
and assert TS
Using the internal arbiter
CLKOUT
BR (Input)
RD_WR
TSIZ[0:1]
BDIP
BG
BB
ADDR[8:31]
DATA[0:15]
TS
(Input)
Minimum
3 wait states
TA (Output)
‘00’
DATA is valid