MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
13-2 Freescale Semiconductor
associated controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch
buffer hits support zero-wait responses. Normal flash array accesses (i.e. those accesses that do not hit in
the prefetch buffers) are registered in the FBIU and are forwarded to the system bus on the following cycle,
incurring at least three wait states (depending on the frequency), with additional wait states being
determined by FLASH_BUICR[RWSC] (see Table 13-14).
Prefetch operations can be automatically controlled, and can be restricted to servicing a single bus master.
Prefetches can also be restricted to being triggered for instruction or data accesses.
The flash memory block is arranged as two functional units, the first being the flash core. The flash core
is composed of arrayed non-volatile storage elements, sense amplifiers, row selects, column selects, charge
pumps, ECC logic and redundancy logic. The arrayed storage elements in the flash core are subdivided
into physically separate units referred to as blocks.
The second functional unit of flash memory is the memory interface (MI). The MI contains the registers
and logic that control the operation of the flash core. The MI is also the interface between the flash module
and the FBIU. The FBIU connects the MPC5553/MPC5554 system bus to the flash module, and provides
all system level customization and configuration functionality.
The flash array has three address spaces. Low-address space (LAS) is 256-KB in size. Mid-address space
(MAS) is also 256-KB in size. High-address space (HAS) is 1.5 MB in size in the MPC5554, and 1.0 MB
in the MPC5553. Total address space is 2.0 MB for the MPC5554 and 1.5 MB for the MPC5553.
Figure 13-2. Flash Array Diagram
Low-Address Space
High-Address Space
Mid-Address Space
Flash Array Blocks
Low-Address Space —256 KB
Mid-Address Space —256 KB
High-Address Space —1.5 MB in the MPC5554
—1.0 MB in the MPC5553
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