MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 14-19
The MII_SPEED field must be programmed with a value to provide an MDC frequency of less than or
equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set
to a non-zero value in order to source a read or write management frame. After the management frame is
complete the MSCR register may optionally be set to zero to turn off the MDC. The FEC_MDC generated
will have a 50% duty cycle except when MII_SPEED is changed during operation (change will take effect
following either a rising or falling edge of FEC_MDC).
If the system clock is 50 MHz, programming this register to 0x0000_0005 will result in an FEC_MDC
frequency of 50 MHz * 1/20 = 2.5 MHz. A table showing optimum values for MII_SPEED as a function
of system clock frequency is provided below.
0 1 2 3 4 5 6 7 8 91011 12131415
R00000000 0 0000000
W
Reset00000000 0 0000000
Address Base + 0x0044
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 DIS_PREAMBLE MII_SPEED 0
W
Reset00000000 0 0000000
Address Base + 0x0044
Figure 14-9. MII Speed Control Register (MSCR)
Table 14-11. MSCR Field Descriptions
Bits Name Description
0–23 — Reserved, should be cleared.
24 DIS_PREAMBLE Asserting this bit will cause preamble (32 1’s) not to be prepended to the MII
management frame. The MII standard allows the preamble to be dropped if the
attached PHY devices does not require it.
25–30 MII_SPEED MII_SPEED controls the frequency of the MII management interface clock
(FEC_MDC) relative to the system clock. A value of 0 in this field will “turn off”
the MDC and leave it in low voltage state. Any non-zero value will result in the
MDC frequency of 1/(MII_SPEED * 4) of the system clock frequency.
31 — Reserved, should be cleared.
Table 14-12. Programming Examples for MSCR
System Clock Frequency MII_SPEED (field in reg) FEC_MDC frequency
50 MHz 0x5 2.5 MHz
66 MHz 0x7 2.36 MHz
80 MHz 0x8 2.5 MHz
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