MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
14-20 Freescale Semiconductor
14.3.4.2.8 MIB Control Register (MIBC)
The MIBC is a read/write register used to provide control of and to observe the state of the MIB block.
This register is accessed by user software if there is a need to disable the MIB block operation. For
example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all
the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See Table 14-3
for the locations of the MIB counters.
14.3.4.2.9 Receive Control Register (RCR)
The RCR is programmed by the user. The RCR controls the operational mode of the receive block and
should be written only when ECR[ETHER_EN] = 0 (initialization time).
100 MHz 0xA 2.5 MHz
132 MHz 0xD 2.5 MHz
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R MIB_DISABLE MIB_IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 1 1 00000000000000
Address Base + 0x0064
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 00000000000000
W
Reset 0 0 00000000000000
Address Base + 0x0064
Figure 14-10. MIB Control Register (MIBC)
Table 14-13. MIBC Field Descriptions
Bits Name Description
0 MIB_DISABLE A read/write control bit. If set, the MIB logic will halt and not update any MIB
counters.
1 MIB_IDLE A read-only status bit. If set the MIB block is not currently updating any MIB
counters.
2–31 — Reserved.
Table 14-12. Programming Examples for MSCR (Continued)
System Clock Frequency MII_SPEED (field in reg) FEC_MDC frequency
To Next Page
Loading...