MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 14-21
0 12345678910 11 12 13 1415
R00000 MAX_FL
W
Reset00000101111 0 1 1 1 0
Address Base + 0x0084
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 FCE BC_REJ PROM MII_
MODE
DRT LOOP
W
Reset00000000000 0 0 0 0 1
Address Base + 0x0084
Figure 14-11. Receive Control Register (RCR)
Table 14-14. RCR Field Descriptions
Bits Name Description
0–4 — Reserved, should be cleared.
5–15 MAX_FL Maximum frame length. Resets to decimal 1518. Length is measured
starting at DA and includes the CRC at the end of the frame. Transmit frames
longer than MAX_FL will cause the BABT interrupt to occur. Receive frames
longer than MAX_FL will cause the BABR interrupt to occur and will set the
LG bit in the end of frame receive buffer descriptor. The recommended
default value to be programmed by the user is 1518 or 1522 (if VLAN Tags
are supported).
16–25 — Reserved, should be cleared.
26 FCE Flow control enable. If asserted, the receiver will detect PAUSE frames.
Upon PAUSE frame detection, the transmitter will stop transmitting data
frames for a given duration.
27 BC_REJ Broadcast frame reject. If asserted, frames with DA (destination address) =
FF_FF_FF_FF_FF_FF will be rejected unless the PROM bit is set. If both
BC_REJ and PROM = 1, then frames with broadcast DA will be accepted
and the M (MISS) bit will be set in the receive buffer descriptor.
28 PROM Promiscuous mode. All frames are accepted regardless of address
matching.
29 MII_MODE Media independent interface mode. Selects external interface mode. Setting
this bit to one selects MII mode, setting this bit equal to zero selects 7-wire
mode (used only for serial 10 Mbps). This bit controls the interface mode for
both transmit and receive blocks.
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