MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 14-23
14.3.4.2.11 Physical Address Low Register (PALR)
The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit MAC
address used in the address recognition process to compare with the DA (destination address) field of
receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte
source address field when transmitting PAUSE frames. This register is not reset and must be initialized by
the user.
28 TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit
is set, the MAC will stop transmission of data frames after the current transmission is
complete. At this time, the GRA interrupt in the EIR register will be asserted. With
transmission of data frames stopped, the MAC will transmit a MAC Control PAUSE
frame. Next, the MAC will clear the TFC_PAUSE bit and resume transmitting data
frames. Note that if the transmitter is paused due to user assertion of GTS or reception
of a PAUSE frame, the MAC may still transmit a MAC Control PAUSE frame.
29 FDEN Full-duplex enable. If set, frames are transmitted independent of carrier sense and
collision inputs. This bit should only be modified when ETHER_EN is deasserted.
30 HBC Heartbeat control. If set, the heartbeat check is performed following end of
transmission and the HB bit in the status register will be set if the collision input does
not assert within the heartbeat window. This bit should only be modified when
ETHER_EN is deasserted.
31 GTS Graceful transmit stop. When this bit is set, the MAC will stop transmission after any
frame that is currently being transmitted is complete and the GRA interrupt in the EIR
register will be asserted. If frame transmission is not currently underway, the GRA
interrupt will be asserted immediately. After transmission has completed, a “restart”
can be accomplished by clearing the GTS bit. The next frame in the transmit FIFO will
then be transmitted. If an early collision occurs during transmission when GTS = 1,
transmission will stop after the collision. The frame will be transmitted again after GTS
is cleared. Note that there may be old frames in the transmit FIFO that will be
transmitted when GTS is reasserted. To avoid this deassert ECR[ETHER_EN]
following the GRA interrupt.
0 123456789101112131415
RPADDR1
W
ResetUUUUUUUUUUU U U U U U
Address Base + 0x00E4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RPADDR1
W
ResetUUUUUUUUUUU U U U U U
Address Base + 0x00E4
1
“U” signifies a bit that is uninitialized.
Figure 14-13. Physical Address Low Register (PALR)
Table 14-15. TCR Field Descriptions (Continued)
Bits Name Description
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