MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 17-45
This operating mode generates a center aligned PWM with dead time insertion in the leading or trailing
edge.
The selected counter bus must be running an up/down time base, as shown in Figure 17-30. BSL[0:1] bits
select the time base. Register A1 contains the ideal duty cycle for the PWM signal and is compared with
the selected time base. Register B1 contains the dead time value and is compared with the internal counter.
For a leading edge dead time insertion, the output PWM duty cycle is equal to the difference between
register A1 and register B1, and for a trailing edge dead time insertion, the output PWM duty cycle is equal
to the sum of register A1 and register B1. MODE[6] bit selects between trailing and leading dead time
insertion, respectively.
NOTE
It is recommended that the internal prescaler of the OPWMCB channel be
set to the same value as the MCB channel prescaler, and the prescalers
should also be synchronized. This allows the A1 and B1 registers to
represent the same time scale for duty cycle and dead time insertion.
When operating with leading edge dead time insertion, the first match between A1 and the selected time
base clears the internal counter and switches the selected time base to the internal counter. When a match
occurs between register B1 and the selected time base, the output flip-flop is set to the value of the EDPOL
bit and the time base is switched to the selected counter bus. In the next match between register A1 and
the selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequence
repeats continuously.
When operating with trailing edge dead time insertion, the first match between A1 and the selected time
base sets the output flip-flop to the value of the EDPOL bit. In the next match between register A1 and the
selected time base, the internal counter is cleared and the selected time base is switched to the internal
counter. When a match occurs between register B1 and the selected time base, the output flip-flop is set to
the complement of the EDPOL bit and the time base is switched to the selected counter bus. This sequence
repeats continuously.
FLAG can be generated in the trailing edge of the output PWM signal when MODE[5] is cleared, or in
both edges, when MODE[5] is set.
At any time, the FORCMA or FORCMB bits are equivalent to a successful comparison on comparator A
or B with the exception that the FLAG bit is not set.
NOTE
When in freeze mode, the FORCMA or FORCMB bits only allow the
software to force the output flip-flop to the level corresponding of a match
on A or B respectively.
If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated,
regardless of the state of the FLAG bit.
0b0011110 Center aligned output pulse width modulation
(FLAG set in both edges, trailing edge dead-time)
0b0011111 Center aligned output pulse width modulation
(FLAG set in both edges, leading edge dead-time)
Table 17-26. Mode of Operation: OPWMC Mode (Continued)
MODE[0:6] Unified Channel Mode of Operation
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