Freescale Semiconductor MPC5553 - Page 730

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 18-23
NOTE
The ETPU_SCMOFFDATAR reset value is the opcode of an instruction that
disables matches, clears the TDLs and the MRLs; the opcode also issues an
illegal instruction Global Exception, and ends the thread.
18.4.2.1.5 eTPU Engine Configuration Register (ETPU_ECR)
Each engine has its own ETPU_ECR. The ETPU_ECR holds configuration and status fields that are
programmed independently in each engine.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ETPUSCMOFFDATA[0:15]
W
Reset1111001101110111
Reg Addr Base + 0x0_0010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ETPUSCMOFFDATA[16:31]
W
Reset0101111111111011
Reg Addr Base + 0x0_0010
Figure 18-8. eTPU SCM Off-Range Data Register (ETPU_SCMOFFDATAR)
Table 18-10. ETPU_SCMOFFDATAR Field Descriptions
Bits Name Description
0 – 31 ETPUSCMOFFDATAR SCM Off-range read data value.
0 1 2 3 4567 8 9 101112131415
R FEND MDIS 0 STF 0 0 0 0 HLTF 0 0 0 0 FPSCK
W
Reset0 0 00000000000000
Reg Addr eTPU A: Base + 0x0_0014 / eTPU B: Base + 0x0_0018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CDFC 0 0 0 0 0 0 0 0 0 ETB
W
Reset0 0 00000000000000
Reg Addr eTPU A: Base + 0x0_0014 / eTPU B: Base + 0x0_0018
Figure 18-9. eTPU Engine Configuration Register (ETPU_ECR)