Freescale Semiconductor MPC5553 - Page 738

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 18-31
18.4.2.2.3 eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)
This register provides visibility of the TCR2 time base for core host read access. This register is read-only.
The value of the TCR2 time base shown can be driven by the TCR2 counter, the angle mode logic, or
imported from the STAC interface, depending on angle mode (an engine cannot import when in angle
mode) and STAC interface configurations set in registers ETPU_TBCR and ETPU_REDCR. For more
information on time bases, refer to the eTPU reference manual.
18.4.2.2.4 STAC Bus Configuration Register (ETPU_REDCR)
This register configures the eTPU STAC bus interface module and operation. For more information on the
STAC interface, refer to the eTPU reference manual.
Table 18-13. ETPU_TB1R Field Descriptions
Bits Name Description
0–7 — Reserved.
8–31 TCR1
[0:23]
TCR1 value. Used on matches and captures. For more information, see the eTPU
reference manual.
0123456789101112131415
R00000000 TCR2
W
Reset0000000000000000
Reg Addr eTPU A: BASE + 0x0_0028 / eTPU B: BASE + 0x0_0048
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RTCR2
W
Reset0000000000000000
Reg Addr eTPU A: BASE + 0x0_0028 / eTPU B: BASE + 0x0_0048
Figure 18-12. eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)
Table 18-14. ETPU_TB2R Bit Field Descriptions
Bits Name Description
0–7 — Reserved.
8–31 TCR2
[0:23]
TCR2 value. Used on matches and captures. For information on TCR2, refer to the
eTPU reference manual.