MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
21-14 Freescale Semiconductor
21.3.3.6 LIN Transmit Register (ESCIx_LTR)
ESCIx_LTR can be written to only when TXRDY is set. The first byte written to the register selects the
transmit address, the second byte determines the frame length, the third and fourth byte set various frame
options and determine the timeout counter. Header parity will be automatically generated if the
ESCIx_LCR[PRTY] bit is set. For TX frames, the fourth byte (bits T7–T0) is skipped, because the timeout
function does not apply. All following bytes are data bytes for the frame. CRC and checksum bytes will
be automatically appended when the appropriate options are selected.
When a bit error is detected, an interrupt is set and the transmission aborted. The register can only be
written again after the interrupt is cleared. Afterwards a new frame starts, and the first byte needs to contain
a header again.
Additionally it is possible to flush the ESCIx_LTR by setting the ESCIx_LCR[LRES] bit.
NOTE
Not all values written to the ESCIx_LTR will generate valid LIN frames.
The values are determined according to the LIN specification.
14 CKIE Checksum error interrupt enable. Generates an Interrupt on a detected checksum error.
For a list of interrupt enables and flags, see Table 21-21.
15 FCIE Frame complete interrupt enable. Generates an Interrupt after complete transmission of a
TX frame, or after the last byte of an RX frame is received. (The complete frame includes
all header, data, CRC and checksum bytes as applicable.) For a list of interrupt enables
and flags, see Table 21-21.
16–22 — Reserved.
23 OFIE Overflow interrupt enable. Generates an Interrupt when a data byte in the ESCIx_LRR has
not been read before the next data byte is received. For a list of interrupt enables and flags,
see Table 21-21.
24–31 — Reserved.
Table 21-7. ESCIx_LCR Field Descriptions (Continued)
Bits Name Description
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