Analog-to-digital converter (ADC) RM0091
198/742 Doc ID 018940 Rev 1
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion:
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 31: Data
alignment and resolution on page 183
0: Right alignment
1: Left alignment
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 2 SCANDIR: Scan sequence direction
This bit is set and cleared by software to select the direction in which the channels will be scanned in
the sequence.
0: Upward scan (from CHSEL0 to CHSEL16)
1: Backward scan (from CHSEL16 to CHSEL0)
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is effective
only when DMAEN=1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 12.6.5: Managing converted data using the DMA on page 184
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
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