RM0091 Direct memory access controller (DMA)
Doc ID 018940 Rev 1 151/742
10.4.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTEIF5 CHTIF5 CTCIF5 CGIF5
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CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
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Bits 31:28 Reserved, must be kept at reset value.
Bits 19, 15, 11, 7, 3 CTEIFx: Channel x transfer error clear (x = 1 ..5)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 18, 14, 10, 6, 2 CHTIFx: Channel x half transfer clear (x = 1 ..5)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 17, 13, 9, 5, 1 CTCIFx: Channel x transfer complete clear (x = 1 ..5)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 16, 12, 8, 4, 0 CGIFx: Channel x global interrupt clear (x = 1 ..5)
This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
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