RM0091 Reset and clock control (RCC)
Doc ID 018940 Rev 1 99/742
7.4.4 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 3 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response
to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set
but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set
and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res Res Res Res Res Res Res Res Res
DBG MCU
RST
Res Res Res
TIM17
RST
TIM16
RST
TIM15RST
rw rw rw rw
151413121110987 6 54321 0
Res
USART1
RST
Res
SPI1
RST
TIM1
RST
Res
ADC
RST
Res Res Res Res Res Res Res Res
SYSCFG
COMPRST
rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
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