RM0091 System configuration controller (SYSCFG)
Doc ID 018940 Rev 1 139/742
Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.
9.1.5 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000
Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.
9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x18
System reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external
interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
other configurations: reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res.
SRAM_
PEF
Res. Res. Res. Res. Res.
PVD_
LOCK
SRAM_
PAR IT Y
_LOCK
LOCUP
_LOCK
rc_w1 rw rw rw
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