Inter-integrated circuit (I
2
C) interface RM0091
510/742 Doc ID 018940 Rev 1
Figure 223. Bus transfer diagrams for SMBus slave receiver (SBC=1)
This section is relevant only when SMBus feature is supported. Please refer to Section 23.3:
I2C implementation.
In addition to I2C master transfer management (refer to Section 23.4.9: I2C master mode)
some additional software flowcharts are provided to support SMBus.
SMBus Master transmitter
When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts will be NBYTES-1. So if the PECBYTE
bit is set when NBYTES=0x1, the content of the I2Cx_PECR register is automatically
transmitted.
MS19870V1
Example SMBus slave receiver 2 bytes + PEC
Address
S
EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd PEC
A
data1
A
data2
A
RXNE
PEC
A
RXNE
P
legend:
transmission
reception
SCL stretch
EV1 EV2 EV3
EV4
ADDR
RXNE
NBYTES
Example SMBus slave receiver 2 bytes + PEC, with ACK control
(RELOAD=1/0)
Address
S
EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 1, PECBYTE=1, RELOAD=1, set ADDRCF
EV2: RXNE-TCR ISR: rd data1, program NACK=0 and NBYTES = 1
EV3: RXNE-TCR ISR: rd data2, program NACK=0, NBYTES = 1 and RELOAD=0
EV4: RXNE-TCR ISR: rd PEC
A
ADDR
data1
A
data2
A
RXNE,TCR
PEC
A
RXNE,TCR
P
legend :
transmission
reception
SCL stretch
3VE2VE1VE
RXNE
EV4
NBYTES
1
3
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