STMicroelectronics STM32F05 series User Manual

Serial peripheral interface / inter-IC sound (SPI/I2S) RM0091
638/742 Doc ID 018940 Rev 1
used for the transfer between the shift registers of the master and slave. The remaining
MISO and MOSI pins pair is not used for communication and can be used as standard
GPIOs.
● Transmit-only mode (RXONLY=0): The configuration settings are the same as for full-
duplex. The application has to ignore the information captured on the unused input pin.
This pin can be used as a standard GPIO.
● Receive-only mode (RXONLY=1): The application can disable the SPI output function
by setting the RXONLY bit. In slave configuration, the MISO output is disabled and the
pin can be used as a GPIO. The slave continues to receive data from the MOSI pin and
its BSY flag is always set while the slave select signal is active (see 26.3.4: Slave select
(NSS) pin management). Received data events appear depending on the data buffer
configuration. In the master configuration, the MOSI output is disabled and the pin can
be used as a GPIO. The clock signal is generated continuously as long as the SPI is
enabled. The only way to stop the clock is to clear the RXONLY bit or the SPE bit and
wait until the incoming pattern from the MISO pin is finished and fills the data buffer
structure, depending on its configuration.
Figure 256. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode)
1. The NSS pin is configured as an input in this case.
2. The input information is captured in the shift register and must be ignored in standard transmit only mode
(for example, OVF flag)
3. In this configuration, both the MISO pins can be used as GPIOs.
Note: Any simplex communication can be alternatively replaced by a variant of the half duplex
communication with constant setting of the transaction direction.
26.3.3 Standard multi-slave communication
In a configuration with two or more independent slaves, the master uses GPIO pins to
manage the chip select lines for each slave (see Figure 257.). The master must select one
of the slaves individually by pulling low the GPIO connected to the slave NSS input. When
this is done, a standard master and dedicated slave communication is established.
shift register
NSS
(1)
NSS
(1)
SPI clock
generator
SCK
MOSI
MISO
SCK
MOSI
MISO
Master
Slave
Vcc
shift register
MS19829V1
(2)

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English