RM0091 Analog-to-digital converter (ADC)
Doc ID 018940 Rev 1 179/742
Note: The trigger selection can not be changed on the fly.
12.5.1 Discontinuous mode (DISCEN)
This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN=1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN=0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.
Example:
● DISCEN=1, channels to be converted = 0, 3, 7, 10
– 1st trigger: channel 0 is converted and an EOC event is generated
– 2nd trigger: channel 3 is converted and an EOC event is generated
– 3rd trigger: channel 7 is converted and an EOC event is generated
– 4th trigger: channel 10 is converted and both EOC and EOSEQ events are
generated.
– 5th trigger: channel 0 is converted an EOC event is generated
– 6th trigger: channel 3 is converted and an EOC event is generated
–...
● DISCEN=0, channels to be converted = 0, 3, 7, 10
– 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10.
Each conversion generates an EOC event and the last one also generates an
EOSEQ event.
– Any subsequent trigger events will restart the complete sequence.
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.
12.5.2 Programmable resolution (RES) - fast conversion mode
It is possible to obtain faster conversion times (t
SAR
) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeroes.
TRG2 TIM2_TRGO 010
TRG3 TIM3_TRGO 011
TRG4 TIM15_TRGO 100
TRG5 Reserved 101
TRG6 Reserved 110
TRG7 Reserved 111
Table 33. External triggers (continued)
Name Source EXTSEL[2:0]