Direct memory access controller (DMA) RM0091
150/742 Doc ID 018940 Rev 1
10.4 DMA registers
Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-
bit).
10.4.1 DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TEIF5 HTIF5 TCIF5 GIF5
rrrr
1514131211109876543210
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
rrrrrrr r r r rrrrrr
Bits 31:28 Reserved, must be kept at reset value.
Bits 19, 15, 11, 7, 3 TEIFx: Channel x transfer error flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 18, 14, 10, 6, 2 HTIFx: Channel x half transfer flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 17, 13, 9, 5, 1 TCIFx: Channel x transfer complete flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 16, 12, 8, 4, 0 GIFx: Channel x global interrupt flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
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