RM0091 General-purpose timers (TIM15/16/17)
Doc ID 018940 Rev 1 387/742
Figure 167. Capture/compare channel 1 main circuit
Figure 168. Output stage of capture/compare channel (channel 1)
Figure 169. Output stage of capture/compare channel (channel 2 for TIM15)
CC1E
Capture/compare shadow register
comparator
Capture/compare preload register
Counter
IC1PS
CC1S[0]
CC1S[1]
capture
input
mode
S
R
read CCR1H
read CCR1L
read_in_progress
capture_transfer
CC1S[0]
CC1S[1]
S
R
write CCR1H
write CCR1L
write_in_progress
output
mode
UEV
OC1PE
(from time
compare_transfer
APB Bus
8
8
high
low
(if 16-bit)
MCU-peripheral interface
TIM1_CCMR1
OC1PE
base unit)
CNT>CCR1
CNT=CCR1
TIM1_EGR
CC1G
Output mode
CNT>CCR1
CNT=CCR1
controller
TIMx_CCMR1
OC1M[2:0]
OC1REF
OC1CE
Dead-time
generator
OC1_DT
OC1N_DT
DTG[7:0]
TIMx_BDTR
‘0’
‘0’
CC1E
TIMx_CCER
CC1NE
0
1
CC1P
TIMx_CCER
0
1
CC1NP
TIMx_CCER
Output
enable
circuit
OC1
Output
enable
circuit
OC1N
CC1E TIMx_CCERCC1NE
OSSI TIMx_BDTRMOE OSSR
0x
10
11
11
10
x0
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Output mode
CNT > CCR2
CNT = CCR2
controller
TIM15_CCMR2
OC2M[2:0]
OC2_REF
0
1
CC2P
TIM15_CCER
Output
enable
circuit
OC2
CC2E TIM15_CCER
OSSI TIM15_BDTRMOE
To th e master mode
controller
TIM15_CR2OIS2
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