RM0091 General-purpose timers (TIM2 and TIM3)
Doc ID 018940 Rev 1 345/742
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
16.4.10 TIM2 and TIM3 counter (TIM2_CNT and TIM3_CNT)
Address offset: 0x24
Reset value: 0x00000000
16.4.11 TIM2 and TIM3 prescaler (TIM2_PSC and TIM3_PSC)
Address offset: 0x28
Reset value: 0x0000
16.4.12 TIM2 and TIM3 auto-reload register (TIM2_ARR and TIM3_ARR)
Address offset: 0x2C
Reset value: 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT[31:16] (TIM2 only)
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CNT[15:0]
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Bits 31:16 CNT[31:16]: High counter value (on TIM2).
Bits 15:0 CNT[15:0]: Low counter value
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR[31:16] (TIM2 only)
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ARR[15:0]
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Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2).
Bits 15:0 ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 16.3.1: Time-base unit on page 293 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.
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