STMicroelectronics STM32F05 series User Manual

Universal synchronous asynchronous receiver transmitter (USART) RM0091
606/742 Doc ID 018940 Rev 1
Figure 248. Reception using DMA
Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.
25.5.16 Hardware flow control and RS485 Driver Enable
It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The Figure 249 shows how to connect 2 devices in this mode:
Figure 249. Hardware flow control between 2 USARTs
RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE
bits respectively to 1 (in the USART_CR3 register).
TX line
USART_DR
Frame 1
RXNE flag
F2 F3
Frame 2
Frame 3
set by hardware
cleared by DMA read
F1
software configures the
DMA to receive 3 data
blocks and enables
the USART
DMA request
DMA reads USART_DR
DMA TCIF flag
set by hardware
cleared
by software
DMA reads F1
from
USART_DR
(Transfer complete)
DMA reads F2
from
USART_DR
DMA reads F3
from
USART_DR
The DMA transfer
is complete
(TCIF=1 in
DMA_ISR)
ai17193b
USART 1
RX circuit
TX circuit
USART 2
TX circuit
RX circuit
RXTX
TX
RX
nCTS nRTS
nRTS
nCTS

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English