EasyManuals Logo

STMicroelectronics STM32F05 series User Manual

STMicroelectronics STM32F05 series
742 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #402 background imageLoading...
Page #402 background image
General-purpose timers (TIM15/16/17) RM0091
402/742 Doc ID 018940 Rev 1
18.5 TIM15 registers
Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions.
18.5.1 TIM15 control register 1 (TIM15_CR1)
Address offset: 0x00
Reset value: 0x0000
1514131211109876543210
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE Res. Res. Res. OPM URS UDIS CEN
rw rw rw rw rw rw rw
Bits 15:10 Reserved, always read as 0.
Bits 9:8 CKD[1:0]: Clock division
This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
DTS
) used by the dead-time generators and the digital filters
(TIx)
00: t
DTS
= t
CK_INT
01: t
DTS
= 2*t
CK_INT
10: t
DTS
= 4*t
CK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:4 Reserved, always read as 0.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt if enabled. These events can be:
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt if enabled
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the STMicroelectronics STM32F05 series and is the answer not in the manual?

STMicroelectronics STM32F05 series Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F05 series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals