STMicroelectronics STM32F05 series - I2 Cx_Timingr Register Configuration Examples; Table 67. Examples of Timings Settings for Fi2 Cclk = 8 Mhz; Table 68. Examples of Timings Settings for Fi2 Cclk = 16 Mhz

RM0091 Inter-integrated circuit (I
2
C) interface
Doc ID 018940 Rev 1 499/742
23.4.10 I2Cx_TIMINGR register configuration examples
Table 67. Examples of timings settings for f
I2CCLK
= 8 MHz
Parameter
Standard mode Fast Mode Fast Mode Plus
10 kHz 100 kHz 400 kHz 500 kHz
PRESC 1 1 0 0
SCLL 0xC7 0x13 0x9 0x6
t
SCLL
200x250 ns = 50 µs 20x250 ns = 5.0 µs 10x125 ns = 1250 ns 7x125 ns = 875 ns
SCLH 0xC3 0xF 0x3 0x3
t
SCLH
196x250 ns = 49 µs 16x250 ns = 4.0µs 4x125ns = 500ns 4x125 ns = 500 ns
t
SCL
(1)
~100 µs
(2)
~10 µs
(2)
~2500 ns
(3)
~2000 ns
(4)
SDADEL 0x2 0x2 0x1 0x1
t
SDADEL
2x250 ns = 500 ns 2x250 ns = 500 ns 1x125 ns = 125 ns 1x125 ns = 125 ns
SCLDEL 0x4 0x4 0x3 0x1
t
SCLDEL
5x250 ns = 1250 ns 5x250 ns = 1250 ns 4x125 ns = 500 ns 2x125 ns = 250 ns
1. SCL period t
SCL
is greater than t
SCLL
+ t
SCLH
due to SCL internal detection delay. Values provided for t
SCL
are examples
only.
2. t
SYNC1
+ t
SYNC2
minimum value is 4 x t
I2CCLK
= 500 ns. Example with t
SYNC1
+ t
SYNC2
= 1000 ns
3. t
SYNC1
+ t
SYNC2
minimum value is 4 x t
I2CCLK
= 500 ns. Example with t
SYNC1
+ t
SYNC2
= 750 ns
4. t
SYNC1
+ t
SYNC2
minimum value is 4 x t
I2CCLK
= 500 ns. Example with t
SYNC1
+ t
SYNC2
= 655 ns
Table 68. Examples of timings settings for f
I2CCLK
= 16 MHz
Parameter
Standard mode Fast Mode Fast Mode Plus
10 kHz 100 kHz 400 kHz 1000 kHz
PRESC 3 3 1 0
SCLL 0xC7 0x13 0x9 0x4
t
SCLL
200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 5 x 62.5 ns = 312.5 ns
SCLH 0xC3 0xF 0x3 0x2
t
SCLH
196 x 250 ns = 49 µs 16 x 250 ns = 4.0 µs 4 x 125ns = 500 ns 3 x 62.5 ns = 187.5 ns
t
SCL
(1)
~100 µs
(2)
~10 µs
(2)
~2500 ns
(3)
~1000 ns
(4)
SDADEL 0x2 0x2 0x2 0x0
t
SDADEL
2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 2 x 125 ns = 250 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x2
t
SCLDEL
5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
1. SCL period t
SCL
is greater than t
SCLL
+ t
SCLH
due to SCL internal detection delay. Values provided for t
SCL
are examples
only.
2. t
SYNC1 +
t
SYNC2
minimum value is 4 x t
I2CCLK
= 250 ns. Example with t
SYNC1 +
t
SYNC2
= 1000 ns
3. t
SYNC1 +
t
SYNC2
minimum value is 4 x t
I2CCLK
= 250 ns. Example with t
SYNC1 +
t
SYNC2
= 750 ns
4. t
SYNC1 +
t
SYNC2
minimum value is 4 x t
I2CCLK
= 250 ns. Example with t
SYNC1 +
t
SYNC2
= 500 ns