STMicroelectronics STM32F05 series User Manual

RM0091 Interrupts and events
Doc ID 018940 Rev 1 157/742
11 Interrupts and events
11.1 Nested vectored interrupt controller (NVIC)
11.1.1 NVIC main features
● 32 maskable interrupt channels (not including the sixteen Cortex-M0 interrupt lines)
● 4 programmable priority levels (2 bits of interrupt priority are used)
● Low-latency exception and interrupt handling
● Power management control
● Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to STM32F05xxx Cortex-M0 programming
manual.
11.1.2 SysTick calibration value register
The SysTick calibration value is set to 6000, which gives a reference time base of 1 ms with
the SysTick clock set to 6 MHz (max f
HCLK
/8).
11.1.3 Interrupt and exception vectors
Tabl e 27 is the vector table for STM32F05xxx devices.
Table 27. Vector table
Position
Priority
Type of
priority
Acronym Description Address
- - - Reserved 0x0000 0000
-3 fixed Reset Reset 0x0000 0004
-2 fixed NMI
Non maskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
0x0000 0008
-1 fixed HardFault All class of fault 0x0000 000C
3 settable SVCall
System service call via SWI
instruction
0x0000 002C
5 settable PendSV Pendable request for system service 0x0000 0038
6 settable SysTick System tick timer 0x0000 003C
0 settable WWDG Window Watchdog interrupt 0x0000 0040
1 settable PVD
PVD through EXTI line detection
interrupt
0x0000 0044
2 settable RTC RTC global interrupt 0x0000 0048

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English