STMicroelectronics STM32F05 series - Figure 207. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1; Figure 208. Transfer Bus Diagrams for I2 C Slave Receiver

Inter-integrated circuit (I
2
C) interface RM0091
486/742 Doc ID 018940 Rev 1
Figure 207. Transfer sequence flowchart for slave receiver with NOSTRETCH=1
Figure 208. Transfer bus diagrams for I2C slave receiver
MS19856V1
Slave initialization
Slave reception
Read I2Cx_RXDR.RXDATA
I2Cx_ISR.STOPF
=1?
No
Yes
I2Cx_ISR.RXNE
=1?
Yes
No
Set I2Cx_ICR.STOPCF
MS19857V1
Address
S
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: RXNE ISR: rd data1
EV3 : RXNE ISR: rd data2
EV4: RXNE ISR: rd data3
A
ADDR
data1
A
data2
A
RXNE
data3
A
RXNE
RXNE
transmission
reception
SCL stretch
EV1
EV2 EV3
Example I2C slave receiver 3 bytes, NOSTRETCH=1:
Address
S
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
EV4: STOPF ISR: set STOPCF
A
data1
A
data2
A
RXNE
data3
A
RXNE
RXNE
P
legend:
transmission
reception
SCL stretch
EV1 EV2
EV3
RXNE
EV4
RXNE