STMicroelectronics STM32F05 series - TIM2 and TIM3 Capture;Compare Register; Tim3_Ccr3); Tim3_Ccr4)

General-purpose timers (TIM2 and TIM3) RM0091
348/742 Doc ID 018940 Rev 1
16.4.15 TIM2 and TIM3 capture/compare register 3 (TIM2_CCR3 and
TIM3_CCR3)
Address offset: 0x3C
Reset value: 0x00000000
16.4.16 TIM2 and TIM3 capture/compare register 4 (TIM2_CCR4 and
TIM3_CCR4)
Address offset: 0x40
Reset value: 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3[31:16] (TIM2 only)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
CCR3[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2).
Bits 15:0 CCR3[15:0]: Low Capture/Compare 3 value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4[31:16] (TIM2 only)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
CCR4[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2)
Bits 15:0 CCR4[15:0]: Low Capture/Compare 4 value
1. If CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4
register (bit OC4PE). Otherwise, the preload value is copied in the active
capture/compare 4 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
2. If CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4).