RM0091 Power control (PWR)
Doc ID 018940 Rev 1 69/742
6.1.3 Voltage regulator
The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
● In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM
● In Standby Mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the Backup Domain.
6.2 Power supply supervisor
6.2.1 Power on reset (POR) / power down reset (PDR)
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits
which are always active and ensure proper operation above a threshold of 2 V.
The device remains in Reset mode when the monitored supply voltage is below a specified
threshold, V
POR/PDR
, without the need for an external reset circuit.
● The POR monitors only the V
DD
supply voltage. During the startup phase V
DDA
must
arrive first and be greater than or equal to V
DD.
●
The PDR monitors both the V
DD
and V
DDA
supply voltages. However, the V
DDA
power
supply supervisor can be disabled (by programming a dedicated option bit
V
DDA_MONITOR
) to reduce the power consumption if the application is designed to make
sure that V
DDA
is higher than or equal to V
DD
.
For more details on the power on / power down reset threshold, refer to the electrical
characteristics section in the datasheet.
Figure 7. Power on reset/power down reset waveform
V
DD
/V
DDA
Reset
40 mV
hysteresis
POR
PDR
Temporization
t
RSTTEMPO